1. Field
Example embodiments relate to a correlated double sampling (CDS) circuit, and more particularly, to a CDS circuit capable of reducing occurrences of parasitic capacitance.
2. Description of Related Art
An image sensor is a device that captures an image by using the characteristics of a semiconductor that reacts to light. In general, the image sensor may be formed using a plurality of unit pixels made of a complementary metal oxide semiconductor (CMOS). Such an image sensor is referred to as a ‘CMOS image sensor (CIS)’.
In general, the CMOS image sensor may be driven according to a correlated double sampling (CDS) method. An output signal of a unit pixel is converted into digital code via an analog-to-digital converter (ADC). The ADC may include the ADC and a plurality of comparators, the total number of which is equal to the total number of columns in a pixel array. The comparators perform conversion of a pixel signal into a digital signal, and thus influence the quality of an output image.
FIG. 1 is a block diagram of a conventional CMOS image sensor circuit 100 that is driven according to the CDS method. For example, the conventional CMOS image sensor circuit 100 includes an active pixel sensor array 11, an ADC 12 that can perform correlated double sampling, a data latch & horizontal decoder 13, a ramp signal generator 14, a row driver 15, and a timing generator 16.
In the ADC 12, a plurality of unit CDS circuits, the total number of which is equal to the total number of columns in the active pixel array 11 may be included. In general, a single-slope ADC may be used because analog output signals of a plurality of pixels of each of columns are simultaneously converted to digital code.
The construction and operation of a CMOS image sensor according to the CDS method as illustrated in FIG. 1 are considered to be commonly known to those of ordinary skill in the technical field to which the present invention pertains, and therefore, a detailed description of a CMOS image sensor will be omitted here.
FIG. 2 is a circuit diagram of a conventional CDS circuit 230. Referring to FIG. 2, the CDS circuit 230 includes a comparator 250 and capacitors C100 and C200.
A unit pixel circuit 310 includes four transistors M1, M2, M3, and M4, and a photo diode D1. The CDS circuit 230 converts an output signal Vin received from the unit pixel circuit 310 into a digital signal through correlated double sampling, by using a ramp signal VRAMP. In the CDS circuit 230, a plurality of switches S100 and S200, two capacitors C100 and C200, and a comparator 250 including an inverter (not shown) are included.
The operation and construction of the CDS circuit 230 illustrated in FIG. 2 are considered to be commonly known to those of ordinary skill in the technical field to which the present invention pertains, and thus, a detailed description of the CDS circuit 230 will be omitted.
Signal attenuation occurring in the CDS circuit 230 when the output signal Vin of the unit pixel circuit 310 is supplied to the comparator 250, and will now be described.
Referring to FIG. 2, in the conventional CDS circuit 230, the comparator 250 indirectly receives the output signal Vin from the unit pixel circuit 310 via the capacitor C200.
Because of the devices (switch S100 and capacitor C200) between output terminal of the unit pixel circuit 310 and input terminal of the comparator 250, a p-n junction, an oxide layer, routing metal, and a metal contact may be generated.
Then, for example, the p-n junction, the oxide layer, routing metal, and the metal contact may cause parasitic capacitors, such as a gate-oxide capacitor and a junction capacitor, generated near the input terminal of the comparator 250.
Generation of a parasitic capacitor near the input terminal of the comparator 250 may cause a loss in the output signal Vin of the unit pixel circuit 310, for example, it may degrade the magnitude of the output signal Vin, and substantially, the degraded signal may be transmitted to the input terminal of the comparator 250. If the parasitic capacitor generated near the comparator 250 is Cpara, a signal Vin1 may be transmitted to the input terminal of the comparator 250 (a third node N300 in FIG. 2) and can be expressed as follows:
                                          Vin            ⁢                                                  ⁢            1                    =                                    (                              Vres                -                Vsig                            )                        ·                                          C                ⁢                                                                  ⁢                200                                                              C                  ⁢                                                                          ⁢                  200                                +                Cpara                                                    ,                            (        1        )            wherein Vres denotes a voltage of a signal output from the unit pixel circuit 310 when a floating diffusion node FD is reset, Vsig denotes a voltage of a signal output from the unit pixel circuit 310 when the transmission transistor M2 is turned on, C200 denotes the capacitance of the second capacitor C200 connected between the input terminal of the comparator 250 and an output terminal of the unit pixel circuit 310, and Cpara denotes the parasitic capacitance generated at the input terminal of the comparator 250.
As image sensors tend to become more miniaturized and have higher definition, the size of one unit pixel, pixel pitch, and the distance between routing lines may be reduced. If pixel pitch and the distance between routing lines are reduced, the capacitance of the parasitic capacitor Cpara may be increased significantly. Thus, a considerable voltage reduction may occur in the signal Vin1 that is an image signal supplied to the comparator 250.
A reduction in the magnitude of an image signal may result in a reduction in the sensitivity of an output image.
Also, the slope of the ramp signal Vramp may need to be lowered by the loss in the output signal Vin1 supplied to the comparator 250. Thus, the magnitude of noise, such as horizontal noise, which is generated by the ramp signal generator 14 may be increased more than the magnitude of the image signal. This is because the magnitude of the image signal is reduced but the magnitude of the noise is not changed, and thus, the noise may become more apparent in the output image.